//--------------------------------------------------------------------------------------------
//    : 
//      Component name  : fpadd_stage6
//      Author          : 
//      Company         : 
//
//      Description     : 
//
//
//--------------------------------------------------------------------------------------------


module FPadd_stage6(OV, SIG_norm2, Z_EXP, Z_SIGN, clk, isINF_tab, isNaN, isZ_tab, zero, FP_Z);
   input         OV;
   input [27:0]  SIG_norm2;
   input [7:0]   Z_EXP;
   input         Z_SIGN;
   input         clk;
   input         isINF_tab;
   input         isNaN;
   input         isZ_tab;
   input         zero;
   output [31:0] FP_Z;
   reg [31:0]    FP_Z;
   
   
   wire          EXP_isINF;
   wire [31:0]   FP_Z_int;
   wire [22:0]   Z_SIG;
   wire          isINF;
   wire          isZ;
   
   
   always @(posedge clk)
      
         FP_Z <= FP_Z_int;
   
   assign Z_SIG = SIG_norm2[25:3];
   
   assign EXP_isINF = ((OV == 1'b1 | Z_EXP == 8'hFF)) ? 1'b1 : 
                      1'b0;
   
   assign isINF = EXP_isINF | isINF_tab;
   
   assign isZ = zero | isZ_tab;
   
   
   PackFP I2(.SIGN(Z_SIGN), .EXP(Z_EXP), .SIG(Z_SIG), .isNaN(isNaN), .isINF(isINF), .isZ(isZ), .FP(FP_Z_int));
   
endmodule
